module uart_monitor(
  input        i_clk,
  input        i_rst,
  input        i_sample,
  input        i_rx,
  output       o_data_ready,
  output [7:0] o_data
);

reg [7:0] d;
reg [9:0] state;

always @(posedge i_clk) begin
  if (i_rst) begin
    state <= 10'b1;
  end else begin
    case (1'b1)
      state[0]: begin
        if (i_sample) begin
          if (i_rx) begin
            state <= 10'b1;
          end else begin // start bit (0)
            state <= 10'b10;
          end
        end
      end
      state[1]: begin
        if (i_sample) begin
          d <= {i_rx, d[7:1]};
          state <= 10'b100;
        end
      end
      state[2]: begin
        if (i_sample) begin
          d <= {i_rx, d[7:1]};
          state <= 10'b1000;
        end
      end
      state[3]: begin
        if (i_sample) begin
          d <= {i_rx, d[7:1]};
          state <= 10'b10000;
        end
      end
      state[4]: begin
        if (i_sample) begin
          d <= {i_rx, d[7:1]};
          state <= 10'b100000;
        end
      end
      state[5]: begin
        if (i_sample) begin
          d <= {i_rx, d[7:1]};
          state <= 10'b1000000;
        end
      end
      state[6]: begin
        if (i_sample) begin
          d <= {i_rx, d[7:1]};
          state <= 10'b10000000;
        end
      end
      state[7]: begin
        if (i_sample) begin
          d <= {i_rx, d[7:1]};
          state <= 10'b100000000;
        end
      end
      state[8]: begin
        if (i_sample) begin
          d <= {i_rx, d[7:1]};
          state <= 10'b1000000000;
        end
      end
      state[9]: begin
        if (i_sample) begin
          if (i_rx) begin // stop bit, should be 1
            //
            //$write("%c", d);
            state <= 10'b1;
          end else begin
            // error
            state <= 10'b1000000000;
          end
        end
      end
    endcase
  end
end

assign o_data_ready = state[9] & i_sample & i_rx;
assign o_data = d;

endmodule
